1. Technical Field
The present invention relates to a memory system and an operating method thereof. More specifically, the present invention relates to a memory system in which precise data is read, and an operating method thereof.
2. Related Art
A semiconductor memory is a memory device implemented using a semiconductor, such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc. The semiconductor is mainly divided into a volatile memory and a nonvolatile memory.
The volatile memory is a memory device which loses stored data when power is interrupted. Examples of the volatile memory include a static random access memory (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), etc. The nonvolatile memory is a memory device which maintains stored data even when power is interrupted. Examples of the nonvolatile memory include a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc. The flash memory is mainly divided into a NOR type flash memory and a NAND type flash memory.
FIG. 1A is a view illustrating a programming operation of 2 bit data in a nonvolatile memory device.
The following description will be made on the assumption that a programming operation is performed in an incremental step pulse programming (ISPP) method. The ISPP method repeatedly performs a programming operation on memory cells by gradually increasing a program voltage, so that the threshold voltage distribution of a memory cell is precisely controlled.
As for a nonvolatile memory device, 1 bit or 2 bit of data may be stored in a single memory cell depending on the demand of a user. In a case that 1 bit data is stored, the memory cells may be divided into a memory cell having a threshold voltage lower than 0 V and a memory cell having a threshold voltage higher than 0 V depending on data stored in the memory cells. In a case that 2 bit data is stored, the memory cells may be divided into a first memory cell having a threshold voltage lower than 0, and second to fourth memory cells each having a different threshold voltage higher than 0 V.
Referring to FIG. 1A, a programming operation includes a first process of programming a least significant bit and a second process of programming a most significant bit. In the first process, a program voltage having a great increase rate is used in order to increase the programming operation speed. Accordingly, the state of a memory cell is changed from an erased state ‘11’ into a programmed state ‘10’. Since a program voltage having a great increase rate is used, the programmed cell has a wide threshold voltage distribution.
The second process of programming a most significant bit is divided depending on the state of a least significant bit and a bit stored as a most significant bit. First, a cell to store a most significant bit of ‘1’ among cells having a least significant bit of ‘1’ (that is, an erased state) is not subject to a programming operation. On the other hand, a cell to store a most significant bit of ‘0’ among cells having a least significant bit of ‘1’ (that is, an erased state) is programmed in a ‘01’ state.
In addition, a cell to store a most significant bit of ‘1’ among cells having a least significant bit of ‘0’ (that is, a programmed state) is programmed as in a ‘10’ state, and a cell to store a most significant bit of ‘0’ among cells having a least significant bit of ‘0’ (that is, a programmed state) is programmed in a ‘00’ state.
FIG. 1B is a view illustrating a program sequence of most significant bit data and least significant bit data of 2 bit data.
Referring to FIG. 1B, first, a memory cell connected to an even bit line BLe and a first word line WL0 is programmed using least significant bit LSB data (0). Thereafter, a memory cell connected to an odd bit line BLo and the first word line WL0 is programmed using LSB data (1). Thereafter, a memory cell connected to the even bit line BLe and a second word line WL1 is programmed using LSB data (2). Thereafter, a memory cell connected to the odd bit line BLo and the second word line WL1 is programmed using LSB data (3). Thereafter, a memory cell connected to the even bit line BLe and the first word line WL0 is programmed using most significant bit MSB data (4). Thereafter, a memory cell connected to the odd bit line BLo and the first word line WL0 is programmed using MSB data (5). At this time, a programming operation on the memory cell connected to the first word line WL0 is completed, and such a programming operation is repeatedly performed in the same manner.
However, when a programming operation is performed in this manner on memory cells connected adjacent word lines or bit lines, interference in a bit line direction and a word line direction may change the threshold voltage distribution of memory cells. Accordingly, each memory cell has a different change in threshold voltage depending on the programmed state of nearby memory cells, and thus wrong data may be read at a read operation of a nonvolatile memory device.